The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
Generally, interconnect structures are used to electrically connect an electronic assembly such as a semiconductor chip with a chip substrate, or electrically connect a semiconductor package with a package substrate. Traditionally, a layout for interconnect structures is based on a layout design of a component being mounted on a substrate. That is, in the examples provided above, the layout for the substrate is defined according to various design contraints or rules of the semiconductor chip or semiconductor package being mounted on the respective chip substrate or package substrate. In other words, the layout on substrates such as chip substrates or package substrates is generally designed to match a previously designed layout for the semiconductor chip or the semiconductor package. Such an approach often leads to costly substrate design to match the design of the component being mounted on the substrate.